This invention relates to a method of providing alignment during electron beam lithography. In particular, it relates to a scheme by which localized changes in an electric field in a resist caused by a feature in a wafer are employed for purposes of achieving alignment. This change in field is utilized by scanning an electron beam across the wafer whereby changes in the induced current are sensed as a function of the location of the feature to provide for registration.
Electron beam (E-beam) lithography has been proposed in a variety of contexts for use in patterning circuits. With the use of VLSI technology. very small dimensions make E-beam lithography a candidate as a potential production tool. While E-beam explorations for purposes of experiments and determinations of feasibility have been reported in the literature.
(1) T. H. P. Chang, M. Hatzakis, A. D. Wilson, A. J. Speth, A. Kern, H. Luhn, "Scanning Electron Beam Lithography for Fabrication of Magnetic Bubble Circuits". IBM Journal of Research and Development, Vol. 20 No. 4, July 1976, pp. 376. PA1 (2) P. J. Coane, P. Rudeck, L. K. Wang, F. J. Hohn, "Electron Beam/Optical Mixed Lithography at Half-Micron Ground Rule", Proceedings of Microcircuit Engineering '86 Interlaken, p. 133 H. W. Lehmann, Ch. Bleiker, North-Holland;
To date, a number of operational problems have inhibited wide-spread commercial realization of this tool. It has typically been used to practice a few patterning steps in a multi-patterning process. In the laboratory environment, E-beam tools have been used to pattern complete devices.
In forming a typical circuit, a multitude of masks are typically employed for the purpose of defining patterns used at various points in the production of the device. Each of the mask levels therefore defines a specific pattern which must be laid over the previously created pattern in a precise manner. This precise technique of positioning various levels is known as alignment. Depending on the techniques which are used in a particular chip fabrication process, all of the mask levels may be done by one technique or another. That is, the candidate techniques may be either E-beam or, optical processing for photolithography. Commonly, optical and E-beam lithography steps may be intermixed. The use of E-beam lithography provides alignment problems which are difficult and critical irrespective of whether the patterning is exclusively E-beam or mixed with another technique. Typically, for E-beam alignment, the location of specific marks, that is alignment marks in the wafers must be made. As the fabrication progresses with the layers being fashioned, it often becomes difficult to locate those alignment marks. That is, as more and more layers are deposited on top of each other, the alignment marks can become buried and hence, potentially unreadable. For example, during a single step of thick planarizing an underlayer in a multilayer resist structure may be necessary or, a thin blocking layer for ion implantation can bury the alignment marks.
A typical technique for locating buried alignment marks is by the detection of back-scattered electrons. In principle, the alignment marks of a sufficiently different back scattering yield from the background and thus they may be detected and observed. However, other considerations often limit the choice of alignment marks resulting in less back scattering contrast than desirable. Typically, an alignment mark is a trench in the silicon wafer which provides per se a back scattering signal.
Given that difficulty, the prior art has suggested a number of other techniques for enhancing the detection of alignment marks. U.S. Pat. No. 3,710,101 generates a well within insulating oxide layers. The well is provided of a selected shape and thickness with the thickness of the oxide at the bottom of the well being relatively thin. By this technique, when a direct current potential between metal coating over the oxide and the underlying silicon wafer is applied, current will flow when an aligning electron beam impinges in the well area in proportion to the area of the well impinged by the electron beam.
U.S. Pat. No. 3,832,560 employs a different type of indicator utilizing cathode luminescence techniques while U.S. Pat. No. 3,832,561 employes Schottky barriers. Finally, U.S. Pat. No. 3,849,659 provides another technique of employing back-scattered electrons. As can be appreciated, all of these techniques require special processing the substrate. In the case of the 101 reference, etching of the well into the oxide is necessary.
Consequently, there exists a need in this technology to define an alignment scheme which can be used in conjunction with E-beam lithography, that is commensurate with contemporary production techniques and does not require a significant amount of "real estate" on the chip for purposes of defining alignment patterns.